This invention relates to a data-array processing system.
The invention is concerned more particularly with a system having a memory for storing an array of data-elements, a processing means which can perform a series of processing operations on data-elements stored in a first section of the memory and which can perform a copying operation after each processing operation in which data-elements are copied from the first section to a second section of the memory, and means for outputting the data-elements in the second section of the memory. More particularly, but not exclusively, the data elements may be pixel data, the processing operations may be pixel rendering operations, the memory may be a video RAM, and the output means may be a monitor which displays the pixel data in the second section of the memory, leaving the first section of the memory hidden.
A problem with such a system as described above is that the copying of a complete image from the second section to the first section of the memory would absorb a significant amount of processor time, especially since it is an operation which would be required continuously in some applications, such as animation.
In accordance with the present invention, the processing means is operable in connection with a processing operation (such as a rendering operation) to set a respective flag indicative of the or each of a plurality of portions of the first (or hidden) section which is modified during that processing operation, and is operable during a subsequent copying operation to copy the or each flagged portion of the first section.
The present invention has evolved from a recognition that in many applications, only a small part of the data-array in the first section is modified in a typical processing operation, and the invention enables only the or each portion making up the modified part to be copied. By reducing the amount of copying which is carried out, a substantial increase in performance can be achieved.
Preferably, after each copying operation, the or each set flag is reset. The data-elements may be arranged to be stored in the memory as a plurality of aligned pages, and in this case a respective flag is provided for each page of data-elements in the first section of the memory. The invention may be employed in a demand-paged dual memory system having a second memory and in which the processing means is operable to transfer data-elements between the first-mentioned memory and the second memory page-by-page. In this case, the processing means is preferably operable in connection with a processing operation to set a respective second flag indicative of the or each page of data-elements which has been modified since that page has been stored in the first memory, and the processing means is operable, when a page in the first memory is to be replaced by a further page from the second memory, firstly to copy the page of data-elements in the first memory to the second memory, but only if the respective second flag is set, before copying the new page from the second memory to the first memory. In this case, preferably upon each copying operation of a page of data-elements from the second memory to the first memory, the second flag for that page of data-elements is reset. The invention may be employed in a system in which each page of data-elements is arranged in the first memory as a plurality of aligned patches of data-elements, with the processing means being operable to perform the processing operations on patches of data-elements stored in the first memory so that a processed patch can comprise data-elements from more than one patch. In this case each first flag preferably has associated therewith at least one further flag which is set when the rendered patch has data-elements in a respective further patch, and the processing means is operable during a copying operation from the first section to the second section of the first memory to copy the or each flagged further group of data-elements.